[Gb-ccb] The designs of the CCB master and slave FPGAs.

Martin Shepherd mcs at astro.caltech.edu
Fri Mar 26 22:28:02 EST 2004


At the beginning of this week, I said that I would provide some design
details for the CCB FPGAs. I haven't got as far as I had hoped, but I
hope that what I have drawn and written so far, will be sufficient for
making a start on the PCB layout. The document containing this info,
can be found at:

  http://www.astro.caltech.edu/~mcs/GBT/ccb_fpga_design.pdf

In time, this document should document the FPGA firmware down to the
final VHDL code. For the moment, it only gets as far as showing the
major components within the master and slave FPGAs, and their internal
and external connections.

Note that I have used two more pins per slave FPGA (ie. 8 pins of the
master FPGA), than in my original FPGA scenarios document. In
principle, I could still get by with the original pin count, but since
there were I/O pins to spare in this scenario, assuming at least 140
I/O pins per FPGA, and because the extra two signals per slave, makes
the programming of the master FPGA much simpler, and makes the parts
more self-contained, I decided to add these now. Even with these
additional pins, the master FPGA will still have 4 spare I/O pins,
which, for contingencies, could either be wired to the slaves, and/or
to a 4 pin header of spare pins.

One question that I haven't researched yet, is whether a soft reset of
the FPGA internals is sufficient, or whether we also need a computer
controlled way of forcing a reload of the FPGA firmware from the
EPROMs. Since the parallel port only provides one reset line, and
reloading the FPGAs shouldn't rely on logic within the FPGAs;
providing both a reload and a soft reset could be problematic. What I
am wondering about is I would first reload the firmware from EEPROM,
then, before it is in a usable state, hit the soft-reset line to reset
all of the components within the firmware to their initial states.

Anyway, this document is very much a work in progress. I am currently
busy working on the internals of the "Data Dispatcher" component.

Martin



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