[Gb-ccb] FPGA design

[Brian Mason]

Dear Martin- We've looked through your master/slave FPGA design document
and have a few comments, most of them minor (below).  Overall this is very
well done and just what we need to get on with the layout-- thanks for
taking such care in the documentation.  Our only major comment is that we
think the approach of having a write-only interface to the device is a
mistake-- this is a view that emerges from long and painful experience
with other devices.  Clearly we don't need or want to do a bitwise
verification of the FPGA program but being able to verify the
configuration parameters is extremely helpful in debugging.

Thanks again for a job well done, notwithstanding these few open issues
this is a significant step forward.

 -Brian

-----------------------

minor comments and questions:

-Is there a plan to load the FPGA program?

-page 10, item 1: suggests that a software command starts a new scan.
Really I suspect the software command "primes" the state generator, which
starts the scan on 1PPS-- is this correct?

-Are the resistors backwards in fig2.1 ? (30.9 vs 18.7 Ohms)

-we need to check if the 10 MHz signal is a square wave or a sine wave, we
think it's the latter.

-Fig 2.1-- we might find a 3.3V driver and thus omit 74LCX125 (we'll look
into that one)

-In figure 1.1-- the 74LCX125 will not properly drive the CLK input, which
requires CMOS logic levels as opposed to TTL logic levels

-Fig 1.1, top integrator-- drawing goof-- phase and clock lines swapped

-fig 1.1-- the FIFO isn't *really* a FIFO (just terminology... it's a
"parallel in, serial out").

-Page 7, discussion of the physical interconnection scheme: no specific
issues just now, but we will want to think about this as we get in to the
layout.


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Brian Mason                           | office: +1(304)456-2338
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