[Gb-ccb] FPGA I/O pin interfacing questions

[Martin Shepherd]

On Tue, 23 Mar 2004, John Ford wrote:
> Many xilinx chips run different I/O and core logic voltage levels.
> The spartan 3 I/O driver supply can be between 2.45 and 3.45 volts.
> Hence, 3.3 volt logic is probably the answer here.
>
> http://www.xilinx.com/bvdocs/publications/ds099.pdf
>
> See the DC and switching characteristics section.

Thanks. The above document doesn't mention TTL in the list of
supported logic interfaces, so it looks as though the ADC clock lines,
the cal and phase-switch outputs, and the parallel port lines will
need external level-shifting buffers. Everything else can do without
any external buffering.

Martin