[evla-sw-discuss] TC11IB, debug connections

[Bill Sahr]

I have been investigating the nature of the debug 
connections needed for the TC11IB development 
board, for our in-house developed TC11IB board, 
and the interaction of these connection schemes 
with software debuggers.

There are two levels of OCDS (on-chip debugging
system).  The first is OCDS1, which is often taken
as equivalent to JTAG because the signals for OCDS1
and JTAG are intermixed & complementary.  OCDS1 is
brought out in two places on the development board 
- on the DB25 connector, referred to as a "wiggler",
and on a 16 pin header.  These two connections,
while providing the same level of debugging 
functionality, are not equivalent.  The wiggler
connection includes circuitry which provides 
protection against voltage peaks and provides
level shifting.  The header is a direct connection
to the OCDS pins on the TC11IB chip with no
peak protection or level shifting circuitry.

OCDS2 is an extension of OCDS1 which provides real-time
execution trace.  It requires OCDS1 plus a 60 pin OCDS2 
connector.  The 60 pin connector is the only connection 
method for OCDS2.  (Just to add to the confusion, I will 
mention that there is an older, slower OCDS2 connection 
standard which uses a 40-pin connector.  This older
standard is still mentioned in some vendor literature, 
and is still available.  The 40 pin connector standard 
has no relevance for us.)

The TASKING debugger supports only OCDS1, and must be
connected to the development board via the wiggler 
(DB25) connector.  Generally, the connection on the host 
end is to the parallel port on a PC running Windows.  
Some of my information indicates that the cable is a direct
parallel port to DB25 cable.  Other information indicates
that Parallel Port/JTAG conversion hardware is required.
I am seeking a definite answer to this issue.  In any case,
it seems clear that the TASKING debugger connects via the
wiggler.  For the parallel port to wiggler connection, the
download speed is approximately 15 Kbytes/sec.  That's
about 100 secs for a 1.5 MB download.  Using this connection
scheme there is no provision for power & reset control.

I have some information that indicates that OCDS1 debugging
supports both the TriCore core and the PCP.

It appears that we should have received the parallel port
to wiggler cable with the development boards.  We did not.
George Peck is investigating the issue of the cables.

The 16 pin OCDS1/JTAG header is used with 3rd party emulator
units.  The emulators do not emulate.  What they do provide 
is minimal, but in some respects useful.  The emulators
provide a higher speed download (~ 140 KBytes/sec), they
provide power & reset control, and they are a necessary
foundation for the addition of the execution trace capability.
Emulator prices seem to fall in the range of ~ $3K to $4K.

For OCDS2, one must buy an emulator and add both the execution
trace module, and a debugger which supports OCDS2.  The TASKING
debugger does NOT support OCDS2/execution trace.  For this
configuration, the emulator connects to the 16-pin OCDS1 header,
the trace module connects to the 60 pin OCDS2 connector,
and the other side of the emulator/trace configuration connects
to a host (usually a PC) which is running the debugger software.
The connection on the PC side can be serial, parallel, USB,
or ethernet, depending on the vendor and options offered.
The default option seems to be parallel port.  

Because it supports execution trace, OCDS2 allows for the
possibility of implementing code coverage and profiling in
software debuggers which support OCDS2.