[Gb-ccb] forwarded message from John Ford

[Martin Shepherd]

On Wed, 21 Jan 2004, John Ford wrote:
>...
> > Beware that my current plan is to run the FPGA from a 40MHz clock, and
> > have the FPGA generate the ADC 10MHz clock from this, by frequency
> > dividing it by 4. This will ensure synchronization between the two
> > clocks.
>
> Wouldn't it be better to use the DCM to multiply the 10 MHz reference
> up to 40 (or whatever!) and drive the FPGA with that for time stamping
> purposes, since the 1 PPS is derived from the 10 MHz?

Assuming that DCM stands for "Digital Clock Multiplier", are you
saying that there is one of these built in to Xilinx FPGAs? If so, is
this a PLL based multiplier, and if not PLL based, does it output a
square wave with a 1:1 mark/space ratio?

Anyway, the bottom-line is that if there is a built-in clock
multiplier, then I will be happy to generate the 40MHz signal from the
GB 10MHz reference. Note that this will require the addition of
another BNC connector on the front panel.

> Maybe it doesn't matter as long as you look at the 1 PPS for
> synchronization and time stamping.

This brings up a dump-mode issue that I hadn't thought about yet.
Whereas the time-stamps of the 1ms integrations didn't need to be any
more accurate than about 0.5ms, dump-mode samples will presumably need
much more precise timestamps. So yes, your point about using a 10MHz
signal synchronized to 1PPS may be important.

My one concern about deriving everything from an external 10MHz clock,
was that having a large 10MHz signal running through a cable from the
front panel, and thereafter on long PCB tracks to both the ADCs and
the FPGA, could lead to 10MHz pickup at the inputs of the ADCs. Using
a 40MHz primary clock, and only deriving 10MHz ADC signals from this,
where needed, was how I planned to reduce the potential for this.

Martin