[Gb-ccb] CCB Status Summary

[Martin Shepherd]

On Wed, 13 Aug 2003, Brian Mason wrote:
>...and reduced maximum integration time.

Thanks for pointing this out. I hadn't checked this, because I didn't
expect any significant change. I now see that in the new scheme the
maximum integration time has gone down by a factor of 8, and clearly I
need to explain this.

It turns out that the reason is that whereas the theoretically
achievable dynamic range is proportional to sqrt(time), and thus to
sqrt(N), where N is the number of ADC samples, the dynamic range of
the accumulated integers goes up linearly with N. Thus the least
significant sqrt(N) bits of this integer aren't significant. Since the
number of ADC samples needed to reach a given integration period
depends on the duration of each ADC sample, this means that the
shorter the ADC sampling interval, the more bits are needed to
integrate up to a given integration time.

Given that the new scheme meets the observing requirements, this
presumably isn't an issue, but if requested to do so, I can use one of
the following measures to restore or exceed the originally advertised
maximum integration time.

1. In principle, the correct thing to do to avoid this problem would
   be to throw away one least significant bit of the integer
   accumulator whenever the number of coadded samples reached an
   integer power of 4.  This would increase the maximum integration
   time to about 30 hours. Although it would be nice to do this, I
   don't know if it would be practically feasible at the 10MHz sample
   rate.

2. The current 25us phase-switch interval is just shy of being an
   integer power of 4 times the 100ns ADC sample period.  So if we
   increased this to 25.6us, then each 25.6us accumulation could have
   its least significant 4 bits discarded before being added to the
   main integration bins. This would reinstate the maximum integration
   time of the previous design.

3. In principle I could accumulate integrations in accumulators with
   more than 32 bits, then throw away the insigificant
   least-significant bits before exporting the integrations to the
   device-driver. The maximum integration time would then depend on
   how many extra bits I allocated per accumulator. Again, I don't
   know how feasible this would be, and it might well need a faster
   and bigger FPGA.

In practice, when I come to programming the FPGA, I will look into
implementing each of these schemes, since they are completely
transparent to the manager. However unless there is a explicit request
to achieve a longer maximum integration time than that currently
specified for the new design, then I will skip this if it turns out to
be too costly.

Martin