[Gb-ccb] CCB Status Summary

[Brian Mason]

Dear all- I thought it would be useful to review the status of the
Caltech Backend project; Caltech has provided the summary which I
include below.

The design seems to be proceeding apace. Caltech will provide us (GB)
with some more documentation soon, at which point we should review the
status again and consider a CDR date- we should also provide some
guidance as to documents required etc.  Some items of note:

-The main change we will see, following Martin's revamping of John
Yamasaki's early hardware design, is the increased sampling rate, and
reduced maximum integration time. This meets our spec but I still need
to review it to make sure I understand the implications.

-Pursuant to the change in the sampling, there are minor changes to
the software interface, which Tim summarizes; otherwise the Jun 16
2003 Server Interface document is valid.

-In light of our tight schedule Martin is giving special attention to
identifying long lead items.

 cheers,
  Brian

=======================================================

The new hardware design is now quite stable, but not yet
documented.  The main change from prior documents is that the A/D
converters will be sampled every 100 ns. In terms of the logic of
operation, the only change is to the bottom section of Fig 3.2 on page
31 of "The Network Interface Between the Ygor Manager and the CCB
Server (Jun 16, 2003)." The "reset integrator" blanking will not be
needed (analog_reset_dt = 0) and the number of samples going into a
100 us measurement will of course be greater. The 1 ms integration
period is not hard-wired: shorter periods may be possible but we
cannot promise that yet; longer periods up to 100 ms (times the number
of phase-switch states) should be possible. Longer averaging need to
be done in the manager, or offline. Some of the internal details in
"The Hardware Interfaces of the CCB (Jan 22, 2003)," especially
Section 4, are no longer relevant and we will prepare a new version of
this document before the CDR.

Martin is working through the detailed hardware design, concentrating
at present on the interfaces - as you will see from the e-mails on the
mailing list. This includes:

Data signal interface; cables and connectors. We have settled the
signal conditioning (filtering) required in the receiver/detector and
Martin is documenting that.

Control signal (phase switch, noise source) interface; cables and
connectors; optoisolators

Differential amplifiers

A/D converters

Circuit board and layout

Voltage reference

10 MHz reference

1 PPS interface

PCI interface chip

FPGA and FPGA program

Real-time computer board; ethernet interface; flash disk; real-time linux

Power supply

Box and packaging; RFI controls

At present I see no obvious hurdles. Martin is working to specify the
exact components to be used and to identify long lead-time items.  We
will circulate a draft Interface Control Document soon, and when that
is done I think we will be ready to set a date for the CDR (it is not
necessary to have the detailed design complete for that). We should
also discuss the documentation to be delivered prior to CDR: that may
be the pacing item.

- Tim