[evlatests] Negative Switched Power!!!

[Ken Sowinski]

On Fri, 27 May 2011, Rick Perley wrote:

>    I can imagine one mechanism which would lead to this:  If the on/off
> durations used to form the values which are then differenced are not of
> equal duration, then there will be an imbalance between the integrated
> 'on' power and 'off power', leading to an offset.
>
>    How sure are we that the 'on' and 'off' durations are precisely equal?

Unless we have an error in implementation this does not explain
negative P_diff.  For each interval of time the FPGA calculates
sum(V_i*V_i) and the number of values 'i' takes on.  It calls
the former Power and the latter data-valid count.  We claim to
provide P_sum and P_diff which are Power divided by the appropriate 
data-vaid count.

The things to look at are whether the NT on and NT off DV counts 
are associated with the correct power measurements.  This could happen
in CMIB software or in the labelling of FPGA registers.