[evlatests] DTS Modules

[Mike Revnell]

Here is a summary of the behavior of the latest software and programmable
logic configurations in the DTS modules. As of today this version is in
antenna 13 and one IF in antenna 16.

There are four control points of interest. I can't remember the exact
combination of random characters comprising their names but they have
the following functions:

Turn on/off formatter board power.
Turn on/off 8 bit digitizer power.
Reconfigure the formatter FPGAs.
Reset the 8 bit digitizer.

There are a few monitor points related to timing and clocks that Kerry
can fill you in on.

When power is applied to the formatter board or the digitizer board the
MIB waits 6 seconds and issues a digitizer reset command.

Logic in the formatter monitors data from the digitizer. If it detects
over-range samples, indicating that logic in the digitizer may not have
reset properly, it issues a reset command to the digitizer. The logic is
disabled for 2 seconds to allow things to settle, it then start checking
again and issues more reset pulses if over range samples are detected.

After 10 consecutive seconds of good data the reset monitoring logic
is disabled so RFI doesn't trigger it.

If the MIB issues a digitizer reset command the monitoring logic is
re-enabled.

If RFI is present causing over range on the digitizer input the reset 
logic will never settle out. In this case it will be necessary to
set the down converter attenuators to get the input in range until the
reset logic can settle out.


NOTE NOTE NOTE PLEASE NOTE

It is not proposed that this is the final behavior of the module.

This behavior is an interim fix to deal with hardware behavior until such 
time as we can implement the full-up monitor and control functionality
in the module. At the present time this is down to about item 15 on the 
list of first priorities.


Mike Revnell
National Radio Astronomy Observatory
Socorro, New Mexico
mrevnell at nrao.edu
revnell at ieee.org