[evlatests] Formatter data capture

[Steven Durand]

The present plan includes data capture in the formatter.  Some firmware 
has already been tested.  The formatter will capture 4096 X 127 bits of 
data from each of the three FPGAs. Is this enough?

The 8 bit option really only uses two of the FPGAs.  Each FPGA contains 
  every other complete 8 bit word.

In the 3 bit mode, each bit is sent to a separate FPGA and are 
reassemble at the correlator interface or in the CMIB.

Where are you'all planning to re-assemble the bits to determine the Down 
Converter attenuator settings?
-- 


Steven Durand, MTS               National Radio Astronomy Observatory
Electronics Division             1003 Lopezville Road
505.835.7103                     Socorro, New Mexico  87801