[evla-sw-discuss] Status of Nucleus port

[Bill Sahr]

The status of the port of Accelerated Technology's Nucleus 
PLUS rtos to the TC11IB chip is that there are still problems 
with the development of the ethernet driver.  The problems 
relating to transmit interrupts not happening, and to 
difficulties in getting the driver to leave the hold state 
after a message has been sent have been solved.  The latest 
difficulty is on the receive end (which I reported incorrectly 
as being on the transmit end in this afternoon's meeting).  
The nature of the problem is briefly described in the two
emails given below.

Bill


-------- Original Message --------
Subject: RE: tc11ib MAC controller
Date: Mon, 30 Sep 2002 07:50:09 -0700
From: Mike.Copeland at infineon.com
To: greg_sandy at mentorg.com
CC: uriah_pollock at mentorg.com, mike_butler at mentorg.com,
bsahr at cv3.cv.nrao.edu,larry_hardin at mentorg.com

Hi Greg,


 I think the problem are due to not switch on the alignment enable bit
(ENA) on DRCONF register, you can set any not aligned address to your
system data buffer, for descriptor should be 16 byte boundaries. If you
not set such, you should make sure you have be 32 bytes aligned of data
buffer.

PLS refer to attaching test example.

Best regards,
Mike


-----Original Message-----
From: Sandy, Greg [mailto:greg_sandy at mentorg.com]
Sent: Thursday, September 26, 2002 1:56 PM
To: Copeland Mike (IFNA AI)
Cc: Pollock, Uriah; Butler, Mike; 'bsahr at cv3.cv.nrao.edu'; Hardin, Larry
Subject: RE: tc11ib MAC controller


Hey Mike,
We are having another problem.  Here is what we are seeing.  We are
receiving packets but are experiencing data drops in the packet
reception.... i.e......


We will receive some packets fine, and then, some not so fine.  When we
look
at the buffer pointed to by the current descriptor, every other 16 byte
block is skipped or missing on the bad packet.  The missing data always
lines up on a 16 byte boundary.

The manual says that the buffer pointed to by the descriptor reside in the
shared memory area, so this leads me to suspect that we might have some
issues with the way that memory region is set up....

This operation is handled by the DMA controller in the MAC, so we are
wondering if we missed some FPI settings or something else not in the
manual.

Simply put, the MAC should DMA the data to the shared memory area pointed
to
by the descriptor, sometimes it works, and sometimes it partially works.

any ideas?

thanks
greg
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