;**************************************************************************** ;* ;* File : main.src (Test) ;* Author : Srikanth ;* Last Update : 16.08.00 ;* Description : Duplex operation, 100 Mbps and cfg3 alignment bit is disabled4 ;* in DRCONF register. ;* Verification Notes ;* ;* Copyright(c) INFINEON TECHNOLOGIES AG 1999 all rights reserved ;* ;* ;***************************************************************************** MAX_SIM_TIME = 400 NO_OF_NOTES = 13 NUM_OF_INTERRUPT = 0 NUM_OF_ERRORS = 18 START_OPTION = 03 START_OPTION = 13 IOC { set ethernet_test 1 } sleep ; this is to write it into the ioc file BM { BOOT b'100 #LOAD SRAM } sleep ASM SRAM { #include "init_ibc32.h" #include "verification.h" write_reg .MACRO label, value LDA a14, label LDD d14, value st.w [a14], d14 .ENDM read_reg .MACRO label LDA a14, label ld.w d14, [a14] .ENDM write_a14_inc4 .MACRO value LDD d14, value st.w [a14+], d14 .ENDM write_a14 .MACRO value LDD d14, value st.w [a14], d14 .ENDM write_a12 .MACRO value LDD d12, value st.w [a12], d12 .ENDM check32r .macro address, register load_a a12, address ld.w d12, [a12] mov d13, register jeq d12, d13, ^_pass load_a a12, TB_REPORT_BASE st.w [a12]VER_D_E_IDX, d13 st.w [a12]VER_D_A_IDX, d12 mfcr d12, #(PC & 0xffff) st.w [a12]VER_CMP_IDX, d12 ^_pass: .endm DT_DATA .equ 0xBFE05008 DT_DESC .equ 0xA0005000 DR_DATA .equ 0xBFE01004 ; code scratchpad SRAM DR_DESC .equ 0xE8405000 ; code scratchpad SRAM DR_DATA_LMB .equ 0xBFE01004 ; code scratchpad SRAM DR_DESC_LMB .equ 0xD0005000 ; code scratchpad SRAM DT_DATA_LMB .equ 0xBFE05008 DT_DESC_LMB .equ 0xA0005004 ; CPU data scratchpad SRAM DATA_SET .equ 0xA0007000 .org 0xD4002000 ; code scratchpad SRAM _main: write32 0xF0180000, 0x00000020 ;comdram configurel _test_again: read32 d5, 0xF0180000 jz.t d5: 5, _test_again write32 BUSCON0, 0x00900000 LDD d15, Int_Vector_Base ; set pointer of irq vector table mtcr # BIV&0xFFFF, d15 isync enable write32 VER_NOTE, 0x1 ;---------------------------------------------------------------------- ;-- load contents of SDRAM for DMUR * ;-- descriptor 1 - 6 for channel 0x00 * ;---------------------------------------------------------------------- ;------------------------------- ; descriptor 1 for channel 0x00 Use by FPI ;------------------------------- load_a a9, DR_DESC_LMB load_d d0, 0x00010100 st.w [a9], d0 load_d d0, DR_DESC + 0x010 st.w [a9]4, d0 load_d d0, DR_DATA + 0x000 st.w [a9]8, d0 load_d d0, 0x00000000 st.w [a9]0xc, d0 ;------------------------------- ; descriptor 2 for channel 0x00 ;------------------------------- load_a a9, DR_DESC_LMB + 0x010 load_d d0, 0x00020100 st.w [a9], d0 load_d d0, DR_DESC + 0x020 st.w [a9]4, d0 load_d d0, DR_DATA + 0x104 st.w [a9]8, d0 load_d d0, 0x00000000 st.w [a9]0xc, d0 ;------------------------------- ; descriptor 3 for channel 0x00 ;------------------------------- load_a a9, DR_DESC_LMB + 0x020 load_d d0, 0x00030600 st.w [a9], d0 load_d d0, DR_DESC + 0x030 st.w [a9]4, d0 load_d d0, DR_DATA + 0x20c st.w [a9]8, d0 load_d d0, 0x00000000 st.w [a9]0xc, d0 ;------------------------------- ; descriptor 4 for channel 0x00 ;------------------------------- load_a a9, DR_DESC_LMB + 0x030 load_d d0, 0x60040100 st.w [a9], d0 load_d d0, DR_DESC + 0x040 st.w [a9]4, d0 load_d d0, DR_DATA + 0x800 st.w [a9]8, d0 load_d d0, 0x00000000 st.w [a9]0xc, d0 ;------------------------------- ; descriptor 5 for channel 0x00 ;------------------------------- load_a a9, DR_DESC_LMB + 0x040 load_d d0, 0x00050100 st.w [a9], d0 load_d d0, DR_DESC + 0x050 st.w [a9]4, d0 load_d d0, DR_DATA + 0x900 st.w [a9]8, d0 load_d d0, 0x00000000 st.w [a9]0xc, d0 write32 P2ALTSEL0, 0x0000ffff write32 P2DIR , 0x000000ff ;LDD d6 , 0x00000000 ;---------------------------------------- ;-- MAC : CAM-RAM ;---------------------------------------- LDA a12, MACCAMDATA LDA a14, MACCAMADDR write_a12 0x56010203 ; write_a14 0x00000000 ; write_a12 0x04055701 ; write_a14 0x00000001 ; write_a12 0x02030405 ; write_a14 0x00000002 ; write_a12 0x03000000 ; write_a14 0x00000003 ; write32 VER_NOTE, 0x2 ;* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ;* ; INITIALISATION OF ALL OTHER BLOCKS ;* ;* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ;* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; RB - init all channels (burst length = 8) ;* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * write_reg RBFPM , 0x00000004 ; RB ch0 write_reg RBCBL , 0x00000002 ; rb_vc_bstl write_reg RBFPTH , 0x00000080 write_reg RBCC , 0x00010000 ; rb_vc_com ;* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; setup DMUR ;* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * write_reg DRMOD , 0x00000000 ; DR MODE_REG write_reg DRFRDA , DR_DESC ; DR FRDA_REG write_reg DRIMR , 0x00000000 ; DR: ICU MASK_REG (all are unmasked) ; write_reg DRCONF , 0x00000002 ; DR CONF1_REG, cfg3 alignment disabled write_reg DRCONF , 0x00000003 ; DR CONF1_REG, cfg3 alignment enabled write_reg DRCMD , 0x00010000 ; DR CMD_REG INIT ch0 write_reg DRSRC , 0x00001020 ; DR: ICU SRN gets x10B0, i.e. SRE for CPU int with prio 01 ;* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; MAC : INIT ;* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * write_reg MACCTRL , 0x00000008 ; MAC: MAC_CTL (LoopBack, EnMissRoll) write_reg MACRXCTRL , 0x0000000D ; MAC: RX_CTL (RxEn, Short/Long0, strip CRC, int. enabled) write_reg MACSMDATA , 0x0000A0B8 write_reg MACSMCTRL , 0x00000FFF write_reg MACCAMCTRL1 , 0x00000003 ; MAC: CAM_ENA (cam-entries 1:0 enabled) write_reg MACCAMCTRL0 , 0x00000014 ; MAC: CAM_CTL (compare mode, accept all address) write_reg DRMOD , 0x00010000 ; DR MODE_REG write_reg MACRXCTRL , 0x0000000D ; MAC: RX_CTL (RxEn, Short/Long0, strip CRC, int. enabled) ;--------------------------------------- ; Transmission Register Initiallization ;--------------------------------------- LDD d0, 0xFFFFFFFF write32 VER_NOTE, 0x3 load_a a0, DT_DATA_LMB load_a a1, DT_DATA_LMB+0x100 load_d d1, 0x00000000 load_d d2, 0x11111111 next_address1: add d1, d2 st.w [a0], d1 add.a a0,#4 jne.a a0, a1, next_address1 load_a a0, DT_DATA_LMB+0x0c load_d d1, 0x002e002e st.w [a0], d1 load_a a0, DT_DATA_LMB+0x100 load_a a1, DT_DATA_LMB+0x200 load_d d1, 0x00000000 load_d d2, 0x11111111 next_address2: add d1, d2 st.w [a0], d1 add.a a0,#4 jne.a a0, a1, next_address2 load_a a0, DT_DATA_LMB+0x0c+0x100 load_d d1, 0x002e002e st.w [a0], d1 write32 VER_NOTE, 0x4 write32 P2ALTSEL0, 0x000000ff write32 P2DIR , 0x000000ff ;------------------------------- ; descriptor 1 for channel 0x00 Use by FPI ;------------------------------- load_a a9, DT_DESC_LMB load_d d0, 0x9000003C st.w [a9], d0 load_d d0, DT_DESC + 0x010 st.w [a9]4, d0 load_d d0, DT_DATA + 0x000 st.w [a9]8, d0 load_d d0, 0x00000000 st.w [a9]0xc, d0 ;------------------------------- ; descriptor 2 for channel 0x00 ;------------------------------- load_a a9, DT_DESC_LMB + 0x010 load_d d0, 0x9000003C st.w [a9], d0 load_d d0, DT_DESC + 0x020 st.w [a9]4, d0 load_d d0, DT_DATA + 0x000 st.w [a9]8, d0 load_d d0, 0x00000000 st.w [a9]0xc, d0 ;------------------------------- ; descriptor 3 for channel 0x00 ;------------------------------- load_a a9, DT_DESC_LMB + 0x020 load_d d0, 0x9000003C st.w [a9], d0 load_d d0, DT_DESC + 0x030 st.w [a9]4, d0 load_d d0, DT_DATA + 0x000 st.w [a9]8, d0 load_d d0, 0x00000000 st.w [a9]0xc, d0 ;------------------------------- ; descriptor 4 for channel 0x00 ;------------------------------- load_a a9, DT_DESC_LMB + 0x030 load_d d0, 0xD000003C st.w [a9], d0 load_d d0, DT_DESC + 0x050 st.w [a9]4, d0 load_d d0, DT_DATA + 0x000 st.w [a9]8, d0 load_d d0, 0x00000000 st.w [a9]0xc, d0 write32 VER_NOTE, 0x5 ; write_reg DTPICUIMR , 0x00000000 ; pcp mask ch 0x00 write_reg DTFTDA , DT_DESC ; first descriptor write_reg DTIMR , 0x00000000 ; CPU mask ch 0x00 write_reg DTCONF , 0x00000001 ; Big Endian write_reg DTCONF3 , 0x00020000 ; max burst = 64, Burst Length write_reg DTSRC , 0x00001024 write32 VER_NOTE, 0x6 ; a short delay created LDD d5, 0x50 _shortdelay10: NOP JNED d5, #0, _shortdelay10 ;* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; MAC : INIT ;* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * write_reg MACCAMCTRL1 , 0x000003FF ; MAC: CAM_ENA (cam-entries 9:0 enabled) write_reg MACCAMCTRL0 , 0x00000010 ; MAC: CAM_CTL (compare mode, accept all address) write_reg MACSMDATA , 0x0000A0B8 write_reg MACSMCTRL , 0x00000FFF write_reg MACTX0IMR , 0xFFFFFFFF ; ; write_reg MACTXCSRC , 0x00001022 ;* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; TB - init all channels with itbs=40h, BTC=2h and TTC=0h ;* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; write_reg TBCPR , 0x00FF0000 ; FTC=1, RTC=1 ; write_reg TBCPR , 0x00FF7700 ; FTC=40, RTC=40 ; write_reg TBCPR , 0x00FF7400 ; FTC=40, RTC=16 write_reg TBCPR , 0x00FF4700 ; FTC=16, RTC=40 write_reg DTCMD , 0x01000000 ; cmd (transmit init), ch 0x00 write_reg TBCC , 0x01000000 ; init, Ch Id 0x00 write32 VER_NOTE, 0x7 ;* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; MAC : TX enable ;* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * write_reg MACTXCTRL , 0x00000001 ; MAC: TX_CTL (TxEn, some interrupts enabled ; Delay in the loop until 3 frames are finished LDA a1, MACTXSTAT LDD d2, 0x00004000 LDD d4, 0x00000000 write32 VER_NOTE, 0x8 wakeup_ethernet load_d d6, 0xffffffff write32 VER_NOTE, 0x9 ;----------------------------- ; a short delay created _shortdelay1: NOP JGE d6, #1, next_compare1 JNE d6, #1, _shortdelay1 next_compare1: check32 DR_DATA_LMB+0x000 , 0x56010203 check32 DR_DATA_LMB+0x004 , 0x04050607 check32 DR_DATA_LMB+0x008 , 0x08090a0b check32 DR_DATA_LMB+0x00C , 0x00C80001 LDA a2, DATA_SET LDA a3, DR_DATA_LMB+0x010 LDD d4, 0x000A _shortdelay2: LD.W d2, [a2] LD.W d3, [a3] check_two_regs d3, d2 ADD.A a2, #4 ADD.A a3, #4 JNED d4, #0, _shortdelay2 write32 VER_NOTE, 0xa ;------------------------------------ ; a short delay created _shortdelay3: NOP JGE d6, #2, next_compare2 JNE d6, #2, _shortdelay3 next_compare2: check32 DR_DATA_LMB+0x104 , 0x56010203 check32 DR_DATA_LMB+0x108 , 0x04050000 check32 DR_DATA_LMB+0x10c , 0x00000001 check32 DR_DATA_LMB+0x110 , 0x002E0001 LDA a2, DATA_SET LDA a3, DR_DATA_LMB+0x114 LDD d4, 0x000A _shortdelay4: LD.W d2, [a2] LD.W d3, [a3] check_two_regs d3, d2 ADD.A a2, #4 ADD.A a3, #4 JNED d4, #0, _shortdelay4 write32 VER_NOTE, 0xb ;------------------------------------ ; a short delay created _shortdelay5: NOP JGE d6, #3, next_compare3 JNE d6, #3, _shortdelay5 next_compare3: check32 DR_DATA_LMB+0x20c , 0x56010203 check32 DR_DATA_LMB+0x210 , 0x04050607 check32 DR_DATA_LMB+0x214 , 0x08090a0b check32 DR_DATA_LMB+0x218 , 0x00640001 LDA a2, DATA_SET LDA a3, DR_DATA_LMB+0x21c LDD d4, 0x0016 _shortdelay6: LD.W d2, [a2] LD.W d3, [a3] check_two_regs d3, d2 ADD.A a2, #4 ADD.A a3, #4 JNED d4, #0, _shortdelay6 write32 VER_NOTE, 0xc ;------------------------------------ ; a short delay created _shortdelay9: NOP JGE d6, #4, next_compare4 JNE d6, #4, _shortdelay9 next_compare4: check32 DR_DATA_LMB+0x800 , 0x56010203 check32 DR_DATA_LMB+0x804 , 0x04050607 check32 DR_DATA_LMB+0x808 , 0x08090a0b check32 DR_DATA_LMB+0x80C , 0x00640001 LDA a2, DATA_SET LDA a3, DR_DATA_LMB+0x810 LDD d4, 0x00010 _shortdelay8: LD.W d2, [a2] LD.W d3, [a3] check_two_regs d3, d2 ADD.A a2, #4 ADD.A a3, #4 JNED d4, #0, _shortdelay8 _shortdelay20: ; a short delay created LDD d5, 0x00050 _shortdelay30: NOP JNED d5, #0, _shortdelay30 ; This count is acc. to the no. of frames JNEI d4, #0x00000003, _shortdelay20 write32 VER_NOTE, 0xd ;------------------------------------ LDA a0,_pass ji a0 ;* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ;* ;* INITIALISATION OF MEMORYS ;* ;* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ;.align 32 .org DATA_SET .word 0x02030405 ; .word 0x06070809 ; .word 0x0A0B0C0D ; .word 0x0E0F1011 ; .word 0x12131415 ; .word 0x16171819 ; .word 0x1A1B1C1D ; .word 0x1E1F2021 ; .word 0x22232425 ; .word 0x26272829 ; .word 0x2A2B2C2D ; .word 0x2E2F3031 ; .word 0x32333435 ; .word 0x36373839 ; .word 0x3A3B3C3D ; .word 0x3E3F4041 ; .word 0x42434445 ; .word 0x46474849 ; .word 0x4A4B4C4D ; .word 0x4E4F5051 ; .word 0x52535455 ; .word 0x56575859 ; .word 0x5A5B5C5D ; .word 0x5E5F6061 ; .word 0x62636465 ; .word 0x66676869 ; .word 0x6A6B6C6D ; .word 0x6E6F7071 ; .word 0x72737475 ; .word 0x76777879 ; .word 0x7A7B7C7D ; .word 0x7E7F8081 ; .word 0x82838485 ; .word 0x86878889 ; .word 0x8A8B8C8D ; .word 0x8E8F9091 ; .word 0x92939495 ; .word 0x96979899 ; .word 0x9A9B9C9D ; .word 0x9E9FA0A1 ; .word 0xA2A3A4A5 ; .word 0xA6A7A8A9 ; .word 0xAAABACAD ; .word 0xAEAFB0B1 ; .word 0xB2B3B4B5 ; .word 0xB6B7B8B9 ; .word 0xBABBBCBD ; .word 0xBEBFC0C1 ; .word 0xC2C3C4C5 ; .word 0xC6C7C8C9 ; .word 0xCACBCCCD ; .word 0xCECFD0D1 ; .word 0xD2D3D4D5 ; .word 0xD6D7D8D9 ; .word 0xDADBDCDD ; .word 0xDEDFE0E1 ; .word 0xE2E3E4E5 ; .word 0xE6E7E8E9 ; .word 0xEAEBECED ; .word 0xEEEFF0F1 ; .word 0xF2F3F4F5 ; .word 0xF6F7F8F9 ; .word 0xFAFBFCFD ; .word 0xFEFF0001 ; .word 0x02030405 ; ETHERNET_INT: .org Int_Vector_Base + (32*32) LDA a5, DRISFIFO LD.W d5, [a5] LDD d10, 0x80010000 JEQ d5, d10, lastline ADD d6, #1 lastline: write_reg DRSRC, 0x00001020 rfe .org Int_Vector_Base + (36*32) LDA a6, DTISFIFO ld.w d7, [a6] write_reg MACTXCSRC , 0x00001022 rfe .org Int_Vector_Base + (34*32) LDA a6, MACTX0ISR ld.w d7, [a6] write_reg MACTXCSRC , 0x00001022 rfe }