[Gb-ccb] FPGA design

[Martin Shepherd]

On second thoughts, I think that I see a way to readback the
configuration registers without disturbing the asynchronous interrupt
mask readback, so I guess I'll do it tvia the EPP port after all. EPP
hardware supports both data reads and address reads, using different
strobe lines for the two modes. So, if I use data reads to read back
the currently addressed configuration register, and address reads to
read the interrupt mask, then this will avoid the race condition that
was worrying me, and I will still be able to read the interrupt mask
from an interrupt handler, without having to use an extra write to say
that this is what I want the FPGA to send me, and without the danger
of breaking up the sequence of single byte reads needed to readback
the configuration registers.

So, in other words, please ignore my previous explanation of why I
didn't want to do this, and instead assume that I will add readback
via the parallel port, as requested.

Martin