[Gb-ccb] FPGA I/O pin interfacing questions

[Martin Shepherd]

Now that I am specifying the external FPGA connections, I am wondering
how one interfaces the I/O pins of a low voltage FPGA to external
higher-voltage devices, and whether FPGA voltage should be one of the
things that I should be considering when selecting an FPGA. The
pertinent I/O connections for the CCB FPGAs are as follows:

1. The ADC data lines. The ADC's data-sheet says that these lines can
   drive either 5V or 3V logic, depending on the voltage at the DRVDD
   power supply input.

2. The ADC clock inputs. These appear to require TTL signals, regardless
   of the voltage presented at the DRVDD input.

3. The parallel port lines. Parallel ports require 5V TTL signals, and
   presumably the connecting cable will require cable drivers.  If so,
   bi-directional drivers will be needed for the data lines, along
   with 2 extra FPGA pins to control their direction and tri-stating.

4. The USB interface chip can be configured for interfacing with
   either 5V or 3V logic.

5. The 1PPS input has a 4V amplitude.

6. What amplitude does the GB 10MHz signal have?

7. The outputs to the differential line drivers that drive the
   cal-diode and phase-switch control cables. The line drivers require
   TTL compatible inputs.

For comparison, the 3 possible Spartan FPGAs have the following supply
voltages:

 Spartan II    2.5V
 Spartan IIe   1.8V
 Spartan 3     1.2V

Since the standard TTL threshold is 1.4V, presumably at least the
Spartan IIe and the Spartan 3 would need external level-shifting
buffer amplifiers to interface to TTL logic. I don't know what the
threshold is for 3V logic.

I've looked at Xilinx's site, but I haven't found much about this,
other than discussion of interfacing Xilinx devices from different
epochs together.

Could somebody who has done this kind of interfacing before, give me
some pointers please?

Martin