[Gb-ccb] CCB interface questions (fwd)

[Martin Shepherd]

In my reply to Melinda's query I unfortunately got the ordering of the
phase-switch bins completely wrong. Sorry for the confusion.
Fortunately Tim's reply reminded me.

The ordering of the phase-switch bins in the data array for a given
ADC, won't be their time order within the phase-switch cycle, as I
incorrectly stated in my previous email, but rather:

        Switch A   Switch B
 Bin 0:   0           0
 Bin 1:   0           1
 Bin 2:   1           0
 Bin 3:   1           1

Where 0 means that the phase switch is off, and 1 means that it is
on. In other words they will be ordered in the binary order of a 2-bit
integer formed by concantenating the boolean control bits of switches
A and B.

Note that there will always be 4 bins per ADC, regardless of how many
phase-switches are enabled. The bins that aren't sampled will simply
hold zeroes. Thus the data array will always contain 64 elements.

Martin