[Gb-ccb] telecon minutes

[Brian Mason]

09mar04

Telecon: RM, MM, JF, GW, BSM (gb)
         TJP, MCS (cit)

0-Actions

*document a more fully fleshed-out architecture (incl FPGA choice) which
GB will review; when agreed GB will start on the layout, and pinouts can
be established (probably after a little thought re: layout) [MCS]

*investigate use of USB chip with the goal of determining if the ones in
hand will suffice [MCS]

*review schedule & constraints, establish tentative review meeting date
[BSM & TJP]

1-software

MCS sees no issues with Melinda's proposed architecture other than the
indicated control-write threading issue (although he's not looked over it
very carefully).  Melinda will send a type file for the makefile (for the
ccb comm library) which Martin will incorporate.  Melinda asked about
latency-- should be much less than a second modulo 1pps-related delays ie
if you are waiting for 1pps (for reconfig). The YGOR system accepts
fractional seconds so 1+delta could work.  Tim forwarded Melinda the list
of errors the ccb-side software can generate.

2- architecture

We agreed the master + 2 or 4 slaves is the best way to go.  Martin
thought programming 4 slaves would be easier, and requires smaller slave
FPGA'S-- also with 4 slaves dumping all 16 bits would be easy; Randy &
John also pointed out that 4 slaves is probably easier to lay out.  The
weight of opinion thus points to M+4S but we will leave the decision up to
Martin as he works out the architecture in more detail. Martin will also
choose an FPGA in the process.

Martin has used all pins in the parallel port in order to implement EPP,
which is easier from the software point of view than just using a couple
of lines.  Data rates over the parallel port would not be high enough to
transfer all our integration data @ 1ms integrations.

Caltech has obtained 6 USB chips but no prototyping board. The linux
kernel driver for this chip supports 300 kB/sec (*just* enough) via a
virtual serial port-- much higher rates can be obtained by talking
directly to the chip so the chip should suffice, but we're not sure how
much work is needed.  MCS will investigate this.

3- detector circuitry

1st prototype has been assembled and static tests are underway in the lab.
A few comparatively minor issues were found: a) the operating currents are
high, consequent to which we've designed step-down circuits to take +/-15
V --> +/-8 V the circuit gets.  b) the bessel filter input empedence is
specced at 75 Ohms but this is at the 3dB point (2 MHz)-- DC you see
infinite ohms (input to ground) and zero ohms (input to output).  Randy is
making some minor adjustments to the circuit to accomadate this.

4- review meeting

Apr 1 is too early-- ~May 1 is more likely.  Tim & Brian will review other
commitments (eg events at GB), review the schedule, and set a tentative
date.