[Gb-ccb] RFI filtering

[Richard Lacasse]

All,

A few more comments...

John Ford wrote:

> Martin Shepherd writes:
>  > Could somebody please clear up a few points that I am perplexed about?
>  > They all regard the shielding and RFI filtering between the ADCs and
>  > the FPGAs.
>  > 
>  > First of all, I am concerned about effects of cable filtering on both
>  > the ADC digital outputs and the ADC clock inputs. The AD9240
>  > data-sheet says that driving significant capacitive loads (in our
>  > case, RFI filters) from the ADC output pins, can cause glitches on the
>  > power-supply inputs, which in turn can degrade SINAD performance; and
>  > that fixing this may necessitate the addition of external buffer
>  > amplifiers. Are such buffer amplifiers included in Randy's design, and
>  > what cutoff frequencies are envisioned for the RFI filters?
> 
> I think that what is needed here is nothing more than a ferrite bead,
> and so I think that we will not need to put big capacitors on the
> lines.

Series resistors would also work on the ADC outputs.  They would work especially 
well if the FPGA inputs were configured as LVCMOS or some similar high impedance 
scheme.  Then the resistor can be large enough to interact with the input 
capacitance of the FPGA.  They also provide isolation all the way to DC.  I'd be 
really careful about filtering the clock line, however.  I agree with Martin 
that we want several harmonics here or we'll run in to timing problems.  A 
ferrite bead of the proper size and material would probably work very well here.

How critical is the sampling phase from one ADC to another???
> 
>  > 
>  > More importantly, what I am really perplexed about, is what purpose
>  > these filters serve, for the following reasons.
>  > 
>  > 1. The ADCs should only be sensitive to signals between 0 and about 12
>  >    MHz, and the only significant signals that can come out of the
>  >    FPGAs are presumably harmonics of 10MHz, given that 10MHz is the
>  >    basic FPGA clock.
> 
> And 10 MHz is going to be the strongest one.  We may want to rethink
> sampling at 10 MHz with a system clock rate of 10 MHz...

 From what I've seen in a variety of RFI tests, the system clock is but one 
small component of the observed spectrum.  You would think it would stand out 
like a sore thumb, but often it does not.  We need to use good layout 
techniques, take adequate precautions, build, test and iterate if necessary.
> 
>  > 
>  > 2. Since the digital signals going to and from the FPGA have basic
>  >    frequencies of 10MHz, and any RFI filter would have to preserve
>  >    both this frequency and a few of its harmonics, to preserve the
>  >    rise and fall times of the signals, and to not delay the signals
>  >    significantly, it seems that a low-pass RFI filter on the lines
>  >    between an FPGA and an ADC wouldn't be filtering out anything that
>  >    the ADCs were sensitive to.
> 
> One problem that rears its ugly head here is spurious rectification of
> the RFI.  Remember than any nonlinear device can act as a detector to
> transform the high-frequency RFI into baseband RFI.  The higher the
> frequency, the more likely you are to find a suitable radiator and/or
> receptor antenna.  So, cutting off the digital signals at 100 MHz or
> so is a reasonable thing to do.  You're right that it won't help your
> direct self-interference problems.
> 
>  > 
>  > If the RFI filtering and shielding could be removed, then the FPGAs
>  > that talk to the ADCs, could be on the same boards as the ADCs. In
>  > particulary, note that in my master-slave FPGA scenarios, this could
>  > be just the small slave FPGAs, with the master FPGA external, to
>  > preserve the 4-way modularity that Randy wants. The ADCs could then
>  > drive the slave FPGAs with short PCB tracks, as in my original design,
>  > without the extra loading of the RFI filters and cables that the new
>  > design adds.
> 
> The FPGA's can be on the same board with proper attention to details.
> Whether or not we want them there is another story.
> 
>  > 
>  > My suggestion, in this case, would be that we have one board
>  > containing a master FPGA, USB interface, parallel port interface and
>  > then on one or both sides of the board have 2 or 4 slave daughter
>  > cards, containing one slave FPGA each, plus the ADCs that they
>  > drive. Being daughter cards, there would be no need for cables, which
>  > would thus remove some potential radiators from the system. The
>  > combined cards would be enclosed in a single shielded box, with
>  > RFI-filtered cables going to the computer and the front-panel
>  > connectors.
> 
> This is a reasonable configuration.  (I haven't looked at the details
> yet...) 
> 
> There needs to be filtering/shielding between the analog and digital
> sections of the device.  If they are all on one board, a metal can,
> ferrite beads, and a bit of luck will do the job.

This configuration seems perfectly reasonable to me, with attention paid to all 
the things that can get us in trouble.  This includes filtering/shielding, 
supply routing and bypassing, board layout, etc.

Rich