[Gb-ccb] RFI filtering

[Martin Shepherd]

Could somebody please clear up a few points that I am perplexed about?
They all regard the shielding and RFI filtering between the ADCs and
the FPGAs.

First of all, I am concerned about effects of cable filtering on both
the ADC digital outputs and the ADC clock inputs. The AD9240
data-sheet says that driving significant capacitive loads (in our
case, RFI filters) from the ADC output pins, can cause glitches on the
power-supply inputs, which in turn can degrade SINAD performance; and
that fixing this may necessitate the addition of external buffer
amplifiers. Are such buffer amplifiers included in Randy's design, and
what cutoff frequencies are envisioned for the RFI filters?

More importantly, what I am really perplexed about, is what purpose
these filters serve, for the following reasons.

1. The ADCs should only be sensitive to signals between 0 and about 12
   MHz, and the only significant signals that can come out of the
   FPGAs are presumably harmonics of 10MHz, given that 10MHz is the
   basic FPGA clock.

2. Since the digital signals going to and from the FPGA have basic
   frequencies of 10MHz, and any RFI filter would have to preserve
   both this frequency and a few of its harmonics, to preserve the
   rise and fall times of the signals, and to not delay the signals
   significantly, it seems that a low-pass RFI filter on the lines
   between an FPGA and an ADC wouldn't be filtering out anything that
   the ADCs were sensitive to.

If the RFI filtering and shielding could be removed, then the FPGAs
that talk to the ADCs, could be on the same boards as the ADCs. In
particulary, note that in my master-slave FPGA scenarios, this could
be just the small slave FPGAs, with the master FPGA external, to
preserve the 4-way modularity that Randy wants. The ADCs could then
drive the slave FPGAs with short PCB tracks, as in my original design,
without the extra loading of the RFI filters and cables that the new
design adds.

My suggestion, in this case, would be that we have one board
containing a master FPGA, USB interface, parallel port interface and
then on one or both sides of the board have 2 or 4 slave daughter
cards, containing one slave FPGA each, plus the ADCs that they
drive. Being daughter cards, there would be no need for cables, which
would thus remove some potential radiators from the system. The
combined cards would be enclosed in a single shielded box, with
RFI-filtered cables going to the computer and the front-panel
connectors.

Martin