[Gb-ccb] FPGA I/O pin usage scenarios

[Martin Shepherd]

Dear all,

In order to help resolve the questions surrounding how many FPGAs will
be needed by the CCB, and in what configuration, I have documented my
best estimates of the number of pins actually needed in the various
configurations. This can be found at

  http://www.astro.caltech.edu/~mcs/GBT/ccb_fpga_scenarios.pdf

A few important points that you will find therein:

1. Of the Spartan 208-pin FPGAs, the Spartan IIE has the most user-I/O
   pins, with 146 pins.

2. Although the FPGA on the CeSys board is a Spartan II, which has 140
   I/O pins, most of these pins are used by the USB 2.0 interface,
   memory etc.., leaving only 65 I/O pins for our use.

3. The pin requirements that I have derived, indicate that the
   configuration with 4 CeSys boards, lacks sufficient I/O pins.

4. In fact, according to my numbers, none of the scenarios using
   between 1 and 4 independent FPGAs, is feasible.

5. The smallest feasible number of FPGAs appears to be 3, arranged in
   a configuration with one master FPGA handling computer
   communication, and generating control signals, while two simpler
   slave FPGAs talk to 8 ADCs each, as directed by the master's
   control signals, and pass their integrated results back to the
   master.

6. The most convenient configuration for dump mode, has 1 master FPGA
   receiving data from 4 smaller slave FPGAs over 16-bit lines (the
   other master/slave configurations have 8-bit inter-FPGA data
   busses).

7. There is one scenario that is not discussed in the above document,
   mainly because I don't know if fast enough FIFOs or latches exist,
   or how much board space they would require, and because it would
   represent another major perturbation to the design. However it is a
   possibility which Dave Hawkins suggested, so it would probably be
   feasible.  This scenario would only use one FPGA. Instead of
   connecting all 16 ADCs directly to the FPGA, one would attach
   15-bit-wide parallel-loaded FIFOs to the ADCs. With 4 ADCs per
   FIFO, and 4 FIFOs, with one 40MHz clock and 1 load line each, the
   FIFO connections to the FPGA would only take 17*4 pins, plus 16 ADC
   clocking pins to interface all 16 ADCs to the FPGA. The FIFO would
   obviously have to be clocked out at 40MHz instead of 10MHz. Adding
   in the USB1.1 interface, parallel port interface, receiver
   interface and the FPGA input clocks and reset line, would bring the
   total pin requirements to around 118 FPGA pins, which would easily
   be accomodated by any of the Spartan FPGAs.

My personal preference is for either the 1 master + 2 slave
configuration, or the 1 master + 4 slave configuration, probably with
the original USB 1.1 interface.

Note that in this document, I have elaborated the use of the parallel
port for the first time. I was hoping to leave this until actually
writing the FPGA code, since there are time-sensitivity issues in my
original FPGA device driver memo which conflict with the use of USB
for sending commands, and I wanted to see how the FPGA code went
together before deciding whether the parallel port would actually be
needed for anything more than its interrupt line. Having thought this
over thorougly at the weekend, I believe that it is, and that the
hardware handshaking of EPP mode is needed to make this reliable and
allow atomic reads from the CCB ISR. This unfortunately adds quite a
few pins to the overall pin count, and turns a few borderline FPGA
configurations into definite impossibilities, but although we could
reduce the number of parallel port pins by a few, by sending
time-insensitive commands over the USB, the reduction wouldn't be
large enough to make much difference, and anyway, right now we need a
worst-case estimate for the sake of unforseen contingencies.

Martin