[Gb-ccb] FPGA choice and configuration

[John Ford]

Tim Pearson writes:
 > The biggest outstanding issue on the CCB design is that we have still
 > not identified which FPGAs to use, or how many, or how to interface
 > them to the computer. Until this is settled we cannot proceed with
 > board layout or FPGA programming. Martin is working on this now, but
 > other input would be welcome.  My understanding of the issues involved
 > is the following:

  <snip>

 > 
 > 1. We haven't been able to identify a development board with a USB
 > interface that would meet our requirements. The CESYS board mentioned at
 > our telecon has a USB 2.0 interface that would probably be fast
 > enough, but it is (apparently) extremely difficult to use. (Martin's
 > comments on this are included below).

There is another option, which would be even simpler than using USB,
and that is to go back to using a PC104+ card setup.  There exist
Xilinx Spartan-II FPGA boards that would work for our use, are
downloadable via the PC104+ bus, and are cheap.  This was discarded
earlier due to concerns of RFI, I believe.  I think that if we
utilized the layered approach that Randy came up with that would not
be a problem.  Some representative PC104/PC104+ boards are:

http://www.associatedpro.com (Several)

http://www.mesanet.com (4I65)

 > 
 > 2. This is driving us to go back to Martin's original idea of laying
 > out one or more FPGAs on our own circuit board, with our own USB
 > interface chip. Martin is the process of acquiring a test setup for
 > the USB interface chip he proposed in an earlier message.
 > 
 > (a) A single FPGA does not provide enough I/O pins unless we go for a
 > ball-grid array, which we are reluctant to do. Multiplexing the ADCs
 > might allow us to use fewer I/O pins but is an added complication.
 > 
 > (b) We can probably do it with 2, 4, or 5 FPGAs on a single board,
 > with one serving as a master handling the USB communications. We need
 > to check the pin count. It is possible that the master FPGA could be a
 > packaged development board, but that would complicate the
 > interconnects between master and slaves.
 > 
 > (c) Using 4 identical FPGAs on separate boards allows for good
 > modularity, as in Randy's proposal, but it would require
 > synchronization (I think we now agree that this would be possible via
 > 1 PPS and 10 MHz). The computer would have to handle 4 USB
 > connections, which might not work under USB 1.1, and the USB protocol
 > would have to include timing to establish synchronization.

If Martin wants a specific USB interface chip, we could lay out our
own boards.  It's not that big a deal.  The trouble is that there is a
great deal of FPGA and device driver software/firmware to write, and
by buying on of the off-the-shelf boards, we get that for free.
Otherwise, Martin must write all the interface software/firmware.

 > 
 > Of these options, we currently favor (b) and Martin is trying  to
 > come up with a concrete proposal, but if you are pursuing other options
 > or think that we should, please let me know.

We're at the point where the software/firmware is driving the
schedule.  I prefer an off-the-shelf solution, but it seems that's
going to be impossible.  I think that if Martin has a plan that makes
it easiest for him to get the programming complete, we should strongly
favor that.
 
 > 
 > An aside: to minimize the pin count, we are assuming that the 2 least
 > significant bits from each ADC will not be passed to the FPGA, even in
 > dump mode (unless we find ourselves with a surfeit of pins). Let me
 > know if this is unacceptable.

It's not unacceptable, but not ideal, either.  We should look at
whether or not this makes the hardware more difficult.

John

  <snip>