[Gb-ccb] 17feb04 CCB telecon minutes

[Martin Shepherd]

On Thu, 19 Feb 2004, Richard Lacasse wrote:
>...
> Also, the phase of the two signals is adjusted via cable lengths if
> necessary so that the synchronizing edge of the high  frequency
> signal and the 1PPS rising edge are not close to each other in time.

How would we do this in the CCB? If we use the site-generated 10MHz,
which I believe is locked to the 1PPS signal, then clearly there will
be a constant phase relationship, but depending on the relative cable
lengths of the 1PPS and 10MHz signals, from where the 10MHz signal is
generated, this phase difference could be anything. If it were right
on the hairy edge, within the setup time of each of the FPGA's
synchronization logic, then neighboring FPGAs could end up off by one
cycle. It seems that fixing this would require some external logic to
delay the 1PPS rising edge to occur just after the next 10MHz rising
edge, before feeding this to the FPGAs.

Martin