[Gb-ccb] 17feb04 CCB telecon minutes

[Richard Lacasse]

All,

Sorry I missed the meeting.  My favorite piece of equipment, the GBT 
Spectrometer, had a hiccup a few minutes before the meeting and I just happened 
to be passing through!

Sounds like a lot of progress is being made.  I just had one comment.  In the 
minutes there was a reluctance expressed to synchronize the FPGA boards with 
only 10 MHz and 1 PPS.  I'd like to point out that VLBI backends have been 
synchronized this way since at least the days of the MKII system back in the 
70's.  Also the Green Bank Spectral Processor, which has been used extensively 
to time pulsars for many years is synchronized this way.  VLBI and pulsar timing 
are both very time critical sciences.  In short this method has been used 
successfully in time critical applications for a long time - it works!

At the risk of being a bit pedantic, let me describe how this synchronization is 
generally done.  The 1PPS signal identifies a particular cycle of the high 
frequency (10 MHz in this case) waveform on which to start a timing counter. 
Generally the epoch of the 1PPS is known relative to the site GPS and, with a 
little work, coordinated universal time.  Also, the phase of the two signals is 
adjusted via cable lengths if necessary so that the synchronizing edge of the 
high  frequency signal and the 1PPS rising edge are not close to each other in 
time.  They maintain this phase relationship over time because they are 
generated from the same source (site maser).  The computer can command the FPGA 
cards to be synchronized by issuing a command shortly after it detects a 1PPS 
interupt.

Rich

Brian Mason wrote:

> 17feb04  Telecon
> 
> present: Tim Pearson, Martin Shepherd; Chuck Niday, Randy McCullough,
> Brian Mason, Melinda Mello
> 
> ------------------------------------
> 
> Agenda
> I-update on GB progress (detector circuit prototype status)
> II-update on CIT progress (FPGA/USB/...)
> III-discussion of the 4-board design proposal (pro & con)
> IV-assorted other issues (software, etc)
> 
> SUMMARY OF RESULTING ACTION ITEMS
> ------------------------------------
> 
> *Consider 4-FPGA synchronization & communication issues and determine
> if there are any showstoppers there, if we need control signals
> distributed between FPGAs, etc. (MCS)
> 
> *Review Cesys spartan-2 board's datasheets and see if it's USB2
> interface will do what we need it to without too much FPGA
> programming, and if there are other currently unidentified
> showstoppers lurking. (MCS/RM)
> 
> *Investigate availability of suitable SBC computers that implement
> USB2 ports (MCS)
> 
> *Examine Cesys spartan-2 pricetag -vs- budget (TJP); assume
> N=4+3+spare+dev't (?)
> 
> *Review CCB Use cases (TJP; BSM & MM)
> 
> *Get Michael on track with the manager, & Martin's simulator (MM & BSM)
> 
> *Determine how to do response time tests on detector circuit (RM/CN)
> 
> =======================================================
> 
> Detailed Meeting Minutes
> 
> I- Randy reported on the detector circuit development effort here.
> Status is: circuit board has been designed, ordered, and received (4
> units); the TTE bessel filters have arrived unexpectedly quickly (4
> units also); and we are in the process of acquiring assorted other
> needed parts.  We expect to assemble next week and will be considering
> how to test the step resonse and other dynamical aspects (first tests
> will be static tests of range, linearity, levels, etc).
> 
> II- Martin has been working on getting up the FPGA programming curve,
> and has completed a 1-channel data pipeline prototype (and, I believe,
> successfully simulated it).  It is not clear where they are on the
> timeline which has the FPGA program done by end-of-March; this largely
> depends on sorting out architecture and computer interface issues.
> 
> 
> III- We went through Martin's list of concerns re: Randy's 4-FPGA
> spartan 3 design.  Some notable points raised were as follows.  1) The
> clear and unanimously agreed upon prime concern is the actual
> achievable USB communication rate with the computer. 2) Martin is
> concerned about having 4 independent FPGAs synchronized only by 1pps
> and 10 MHz, and would rather see control signals redistributed to each
> FPGA.  We didn't resolve this one and it bears more consideration.  3)
> Availability of a single-board computer which implements USB2.0 is
> another potential issue which needs to be looked into.  4) As to why
> there is an extra enclosure around the Analog/FPGA unit, Randy
> indicated this was chosen with other possible applications in mind
> (this isn't a critical issue for the scheme either way); 5) the
> question of how filtering will be done between the FPGA and the ADC
> was raised.  Randy indicated surface mount pi filters could be used,
> with the addition of little cans soldered over the sensitive analog
> bits if needed.
> 
> We briefly discussed the new Cesys spartan-2 board Randy has found (to
> possibly replace the spartan-3 development board).  This has fewer
> gates (but 1 MB onboard fast RAM which may offset the loss), and
> probably enough inputs per FPGA.  The main advantage of this board is
> that it advertises fully implemented USB2.0 , although we need to
> carefully examine the datasheets to determine what the FPGA interface
> is and what sort of datarates we expect to achieve in practice with
> it.  It doesn't seem there are clock multipliers on the spartan-2
> which is a disadvantage (harder to use an external clock reference).
> The price (~$750) also needs to be considered.  If the price and USB
> factors aren't prohibitive we can probably go this route, though this
> isn't a given now.
> 
> IV- Other
> 
> *Tim indicated that Christobal Acherman still plans to arrive at the
> end of March.
> 
> *Brian filled in CIT as to the plans to have Michael work on the YGOR
> manager. Melinda Mello will be helping in this.
> 
> 
>