[Gb-ccb] forwarded message from John Ford

[Martin Shepherd]

On Wed, 21 Jan 2004, Martin Shepherd wrote:
> On Wed, 21 Jan 2004, John Ford wrote:
> >...
> > > Beware that my current plan is to run the FPGA from a 40MHz clock, and
> > > have the FPGA generate the ADC 10MHz clock from this, by frequency
> > > dividing it by 4. This will ensure synchronization between the two
> > > clocks.
> >
> > Wouldn't it be better to use the DCM to multiply the 10 MHz reference
> > up to 40 (or whatever!) and drive the FPGA with that for time stamping
> > purposes, since the 1 PPS is derived from the 10 MHz?
>
> Assuming that DCM stands for "Digital Clock Multiplier", are you
> saying that there is one of these built in to Xilinx FPGAs? If so, is
> this a PLL based multiplier, and if not PLL based, does it output a
> square wave with a 1:1 mark/space ratio?

To answer my own question, the acronym, DCM, apparently stands for
Digital Clock Manager, and there are 4 of these in the Spartan 3 FPGA
that we are planning to use. I have checked the Xilinx App note
pertaining to this, and using the PLL frequency synthesis part of one
of these entities, we could indeed multiply an external 10MHz signal
up to 40MHz. I will thus plan on the FPGAs using a 10MHz external
clock signal, and have them multiply this internally to 40MHz.

Martin