[Gb-ccb] Caltech Backend Telecon Monday 07 July 4pm EDT
Brian Mason
bmason at gb.nrao.edu
Wed Jul 2 21:00:07 EDT 2003
Hi all- This message is to confirm that we'll have a telecon on Monday
at 4pm EDT. I have included some material that Caltech has provided
below which gives a useful summary of the changes Martin has made in
John Yamasaki's design and some of the concerns they are working to
address.
I've also created a mailing list (above) which I'd encourage you all
to use. Basically any "general discussion" or "request for
information" type message should be sent to this list. When I figure
out the administrative options, the archives will be available online,
and linked from my gbt instrumentation development homepage.
cheers,
Brian
=======================================================
Some Specific Questions Caltech has Raised-- to be discussed in
upcoming (Monday 07jul 4pm) videocon.
-The frequency and time responses of the detectors, with particular
emphasis on the time-domain step-responses of the detectors at
phase-switching transitions.
-How much noise is generated by the detectors and post-detection
amplifiers? They need this in order to determine how
much noise the analog electronics in the backend can add without
compromising the noise floor set by the receiver noise temperature and
the integration time.
-The choice of signal cabling between the receiver and backend boxes.
Some options include:
Multi-pair twisted-pair or parallel-pair cables with both
individual and overall shielding. For example, Amphenol
"Skewclear" parallel-pair cable boasts -70db near-end-crosstalk
between neighboring pairs.
Multiple separate coaxial cables with SMA connectors at each
end.
Multiple separate twinaxial differential cables.
-Assuming that twisted-pair or parallel-pair cables are chosen, would
it be best to use a single 16-pair cable for all of the signals
coming from the receiver, or assign separate 4-pair cables to each
of the bands?
-Alternatively, if separate coaxial or twinaxial cables are chosen,
how can they be bundled in such a way that their proximity doesn't
compromise the crosstalk isolation?
-Should the shields of the signal cables be connected to the cases of
both the backend and receiver boxes, or just to the case of the
receiver box? Coaxial cable shields almost certainly shouldn't be
connected at both ends, but those of twisted pair cables potentially
could be.
-If the shields aren't to be connected to the backend case, what would
be the best method of insulating the connectors from the case
without compromising the RFI shielding of the case?
-Similarly, should the shields of the digital control cables be
connected to both cases, or just to the case of the backend? Since
these will be twisted pair cables carrying differential digital
signals, the question here isn't whether ground loops might affect
the control signals themselves, but rather whether digital transients
in the backend might get coupled into the backend case, and from
there into the receiver case via the cable shields.
-If coaxial cables are chosen, then probably I would have the sma
inputs connect to 50-Ohm anti-aliasing filters. Some of the filters
that I might use for this, have high VSWRs in their stop-bands.
Would this be a problem?
-Are there any concerns regarding my new scheme of using a low-pass
filter and a 10MHz ADC, instead of an analog integrator and a 40KHz
ADC?
=======================================================
Some that general background Martin has provided:
Most of the proposed topics of next week's telecon revolve around a
revision of the design of the CCB electronics. This change in
direction followed John Yamasaki leaving Caltech, and myself taking on
responsibility for the CCB electronics. Since then I have identified a
number of weaknesses in the original design, and I am now attempting
to address these issues. The following is a list of these issues, and
how I intend to tackle them.
1. Simplifying the analog electronics.
In the original design we were planning to use analog integrators
to integrate for 25us before digitizing, then digitally integrate
upwards of 1ms of these 25us samples within an FPGA. This presented
a couple of challenges.
A. To maximize the on-source integration time, the capacitors of
the analog integrators needed to be discharged within a very
short time, at the end of each 25us sample. Since we were
aiming for an SNR of 84dB (14 bits) within 25us, this meant that
the capacitors had to be discharged by 84dB within < 1us, in
order to avoid a residual signal from one sample contributing to
the next sample. Since most analog switches have switching
times of hundreds of nanoseconds, and one needs to both switch
on and then off to reset an integrator capacitor and start
integrating again, and since FET switches typically have
on-resistances of a few tens of Ohms, this is challenging.
B. Because of the 84dB SNR achievable within 25us for the predicted
noise temperatures of the 1cm and 3mm receivers, the analog
integrators and the amplifiers that interfaced them to the ADCs
had to be very low noise circuits with high precision.
To counter both of these problems, I am now investigating an
alternate approach. This involves digitizing samples every 100ns
instead of every 25us, and using a low-pass anti-aliasing filter
instead of an explicit analog integrator. This approach potentially
addresses the above two concerns as follows.
A. Although a low-pass filter is much worse than an analog
integrator in terms of leakage of one sample into the next, as
long the low-pass filter doesn't take more than ten 100ns ADC
sampling intervals to settle to 84dB of a stepped input signal,
the time lost at phase-switching transitions because of this,
won't be more than the 1us that we were aiming for with the
analog integrators. Furthermore, whereas in the old scheme one
lost data resetting the integrator every 25us, in the new
scheme, the corresponding filter settling time would only be an
issue whenever the phase-switches were toggled. This is
particularly relevant to the 3mm receiver, where four
consecutive 25us samples were to be taken for each phase-switch
state. Thus the new scheme potentially increases the on-source
integration time that is achievable.
The one big unknown at the moment is whether available low-pass
anti-aliasing filters actually do have settling times that meet
these needs. Unfortunately I haven't been able to find a
manufacturer that will tell me the time-domain response of their
filters.
B. By digitizing at a much higher rate, the noise floor required of
the analog electronics that precede the ADCs can be 16 times
higher than that of the old design, and the ADCs can be
correspondingly less precise. Whereas 14 bits of precision were
needed at 25us, 11 bits should be more than sufficient at 100ns.
Actually an ADC with 12-bits of effective resolution will need
to be used, because high-performance ADCs are designed to have
0v placed in the center of the ADC input range, where the noise
performance is optimized for small signals, whereas our
square-law detected signals are restricted to positive voltages.
For the same reason the choice of a 14-bit ADC in the original
design was flawed.
2. Signal-transmission, shielding and grounding issues.
In the original design proposal, the detected signals from the
receiver were to be transmitted to the backend via 16 coaxial
cables plugged into SMA connectors at both ends. The SMA connectors
in the backend were to be both bolted to the metal case of the CCB,
and soldered to the main PCB. This struck me as being a problematic
approach, both because of the potential for inter-ground signals
getting coupled into the input signals via the cable shields, and
because any digital currents flowing in the backend case, would be
coupled into the case of the receiver, again via the cable
shields. In addition, since 60Hz power-line interference picked up
on the cable shields would have been seen as a real signal, it
would appear to make more sense to use shielded twisted-pair cables
than unbalanced coaxial cables.
There are thus two main alternatives that I have been considering.
1. We could continue to use 16 coaxial cables, but connect these to
the backend using SMA connectors that aren't grounded to the
case. The unbalanced signals received by the backend would then
be treated differentially, rather than being referred to ground.
This would solve the inter-case grounding issues, but could be
hard to implement without compromising the RF shielding of the
backend case. It also wouldn't address the potential problem of
magnetically induced 60Hz interference getting into the signals
via the cable shields.
2. The use of up to four cables, each one containing multiple,
individually shielded twisted-pair cables, and each twisted-pair
carrying a balanced differential signal, not referred to the
grounds of either the receiver or the backend.
In this case the cable shields could potentially be connected at
both ends, without introducing inter-ground signals into the
differential signals. However this probably isn't advisable,
since there would then still be the potential for digital signal
currents finding their way from the case of the backend to that
of the receiver.
This approach would have better immunity to 60Hz magnetic pickup
than the coaxial approach, and would be significantly easier to
hook up. Taken to the extreme, a single cable with HD50
connectors at both ends could be used to connect all of the
detector signals.
In comparing these approaches it is also necessary to consider the
potential for crosstalk between neighboring signal-cables. This is
difficult in the coaxial approach, because the 16 separate coaxial
cables would probably be tied together in a bundle, and predicting
the crosstalk of this would be difficult. On the other hand, the
crosstalk of the multi-pair twisted-pair cables can be taken
directly from the cable-manufacturer's data-sheets, after making
allowances for crosstalk in the connectors.
3. Simplifying the FPGA design.
In the original scheme, the control of the ADCs and the analog
integrators was complicated by the need to insert delays to counter
phase-switching transients and integrator resetting times. In the
new scheme, the ADC would run continuously in a loop with no delays
between samples, and phase-switching delays would be accommodated by
simply throwing away samples after they had been measured. The
required digital logic is thus potentially much simpler, and
nothing is lost, since the 100ns ADC sampling period is identical
to the granularity of the delays in the original design.
4. Improved flexibility.
Because digitization occurs at an earlier stage in the new design,
some problems that would have required rebuilding the PCB in the
original design, will be fixable in the new approach simply by
reprogramming the FPGA.
Martin
--
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Brian Mason | office: +1(304)456-2338
Assistant Scientist | fax: +1(304)456-2229
National Radio Astronomy Observatory | mail: PO Box 2
bmason at gb.nrao.edu | Green Bank, WV 24944
http://www.gb.nrao.edu/~bmason/ |
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