[evlatests] 3bit digitizer / sampler clock jitter

[Vivek Dhawan]

Fallout from yesterday's meeting: I had looked at the phase noise
by subband for the 3bit data, did not see a trend, and dismissed it.

Prompted by Barry's comments, I looked harder in the right place, on
ea22 RCP, and see evidence of clock jitter: the phase noise goes up at 
frequencies away from the baseband edge, dominating the thermal noise
a few 100 MHz into the BB. This is on 2GHz wide data, from yesterday,
before the cable swaps.

This effect is very clear on 22 R, (now back in the lab), but it may
be present at lower level on the remaining 3-bit paths.

----------------

Here are some plots that purport to clinch this case, unfortunately
they require wordy captions:

Both plots show phase +_15 degrees, vs. time ~3 minutes.

plot 1. Blue is for a good baseline, 12-15, subband 2, phase difference
between RR and LL, so L301, L302, atmosphere are common-mode and cancel.
i.e. the noise shows how much worse RR phase is, compared to LL.

Red trace is the baseline 15-22, much worse!

For the setup at hand, C band, 2GHz 3bit, subband 2 is farthest from BB
edge, subband 14 is closest, verified to be clean of RFI. And, as expected
for clock jitter, subb 3,4,8,9,14 are progressively better, but still not
as good as the corresp ones from the good baseline. (not shown in plot)

plot 2. shows 2 adjacent subbands, 2&3, from the bad baseline, 15-22,
the extra noise is highly correlated between subbands, so it is not
front end noise, it is there on every subband and scales with subband
offset as above. (red/blue overlap makes green in this plot)

Vivek.
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