[evlatests] Formatter data capture

[Ken Sowinski]

> The present plan includes data capture in the formatter.  Some firmware 
> has already been tested.  The formatter will capture 4096 X 127 bits of 
> data from each of the three FPGAs. Is this enough?

that is about 65000 (4096*127/8) samples per fpga which is 
more than enough.  If BW between MIB and FPGA is an issue we 
could get by with a lot less.  A factor of ten less is just OK; 
a factor of 100 is too few bits.  We need a collection of at least
10,000 samples to get reasonable statistics.

> The 8 bit option really only uses two of the FPGAs.  Each FPGA contains 
>   every other complete 8 bit word.
> 
> In the 3 bit mode, each bit is sent to a separate FPGA and are 
> reassemble at the correlator interface or in the CMIB.
> 
> Where are you'all planning to re-assemble the bits to determine the Down 
> Converter attenuator settings?

there are of course two sets of 3 bit values.  It makes sense to
reassemble the bits into values in the DTS MIB as well as do some
simple statistics there.

Ken