[Difx-users] Change for 4- and 8-bit VDIF {External}

[Mark Kettenis]

> Date: Wed, 19 Feb 2025 21:17:42 -0700
> From: Walter Brisken via Difx-users <difx-users at listmgr.nrao.edu>

Hi Walter, Chris,

We came to the same conclusion that "symmetrical" was preferable.
Even for 8-bit data.  And I believe we've managed to convince the
DBBC3 firmware writers to implement its 8-bit mode that way.  I think
that makes sense if your backend does significant digital processing
of the samples that involve resampling of some sort anyway.

However if you're just recording samples directly out of your sampler
with minimal processing (i.e. just removing some least-significant
bits to reach the desired bit-depth) you have to take what the
hardware gives you and that may very well be a "non-symmetrical"
representation.

We did specify in VDIF that samples are understood to be
"offset-binary".  I think we did consult some digital engineers on
that subject and that was the way most samplers worked at the time.
But of course we didn't specify what the expected offset was...

Anyway, I fear that at some point you (and we for SFXC) will need to
make this configurable.  As I said the DBBC3 does (or will) use the
"symmetrical" layout for 8-bit data.  And as soon as you make this
configurable it is probably best to make the default consistent across
all bit-depths.  I think the VEX2 $DAS block is probably where I would
put the details about the samplers.

Cheers,

Mark

> Hi all again,
> 
> Chris Phillips wrote to me with a good case for not changing the 8-bit 
> case and I have since reversed that change.  We both agree that with 
> only 16 states in the 4-bit case the change should take hold.  Thus at 
> the current time the only net change is to the 4-bit case.
> 
> We will be looking to formalize clarification on these sampling issues 
> in an update to the VDIF format specification.  It would be useful to 
> know of existing use cases of 4- and 8-bit VDIF to help inform how this 
> specification should be solidified.
> 
> -Walter
> 
> On 2/19/25 4:39 PM, Walter Brisken via Difx-users wrote:
> > Hi DiFX users,
> >
> > The mark5access library in the difx software suite contains the 
> > routines to reconstruct a VDIF stream into voltage samples.  Since 
> > support of 4- and 8- bit VDIF was introduced into this library, which 
> > probably dates back to around 2013 or so, these two modes have used an 
> > asymmetric mapping of reconstructed values.  That is, in the case of n 
> > bits per sample, the reconstructed value corresponding to sample state 
> > 2^(n-1) was zero (mimicking the values that a signed integer can 
> > take).  This is not the case (and never has been) for 1 and 2 bit 
> > VDIF.  The VDIF specification does not specify the mapping of sample 
> > state to reconstructed value (unless I am missing it), but I am 
> > convinced that the symmetric output is the more useful and least 
> > surprising way to proceed. This also provides one additional useful 
> > situation within mark5access: it allows decoded invalid packets to be 
> > reconstructed as zero and be unambiguously interpreted as such.
> >
> > I have just put in a change to mark5access to symmetrize the 
> > reconstructed values for 4- and 8-bit VDIF (both real and complex).  
> > No change was made to the 1- or 2-bit cases.
> >
> > The effect of assuming one mapping and using the other is the 
> > introduction of a fixed DC offset in the output values.  This is how 
> > the pre-existing behavior was identified.
> >
> > Please let me know if you have questions or concerns.
> >
> > -Walter
> >
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