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<p class="MsoPlainText">I did send this to only Walter and Chris but I’ll give it a wider audience.<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">The list of AVX-512 optimised IPP routines is maintained here.
<a href="https://software.intel.com/en-us/articles/intel-ipp-functions-optimized-for-intel-avx-512">
https://software.intel.com/en-us/articles/intel-ipp-functions-optimized-for-intel-avx-512</a> and now has a section on Skylake "Intel® Xeon® Processor Scalable Family".<o:p></o:p></p>
<p class="MsoPlainText">The list also keeps growing, see the release notes here. <a href="https://software.intel.com/en-us/articles/intel-ipp-release-notes-and-new-features">
https://software.intel.com/en-us/articles/intel-ipp-release-notes-and-new-features</a><o:p></o:p></p>
<p class="MsoPlainText">If there is any particular IPP routine missing that you need then let me know and I can contact the developers.<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">Just a note on the "bronze (31xx)", "silver (41xx)", "gold (51xx,61xx)", or "platinum (81xx)". The 61xx and the 81xx CPUs have two AVX-512 execution units per core, as opposed to one on the 31xx/41xx/51xx, and so performance of them
will be better on AVX-512 optimised workloads.<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">Do you have a "recommended configuration" or an idea of what you would need to run a benchmark? If no one has access to a system I can try and arrange this.<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">Regards, Peter Kerney.<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">----------------------------------------------<o:p></o:p></p>
<p class="MsoPlainText">Peter Kerney, Enterprise Solution Architect<o:p></o:p></p>
<p class="MsoPlainText">Intel Australia Pty Ltd<o:p></o:p></p>
<p class="MsoPlainText">Level 17, 111 Pacific Highway<o:p></o:p></p>
<p class="MsoPlainText">North Sydney NSW 2060 Australia<o:p></o:p></p>
<p class="MsoPlainText"><a href="mailto:peter.kerney@intel.com">peter.kerney@intel.com</a><o:p></o:p></p>
<p class="MsoPlainText">Ph: +61299375981<o:p></o:p></p>
<p class="MsoPlainText">Mb: 0407013230 (+61407013230)<o:p></o:p></p>
<p class="MsoPlainText">----------------------------------------------<o:p></o:p></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><a name="_MailEndCompose"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US"><o:p> </o:p></span></a></p>
<p class="MsoNormal"><a name="_____replyseparator"></a><b><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif"> Difx-users [mailto:difx-users-bounces@listmgr.nrao.edu]
<b>On Behalf Of </b>Richard Dodson<br>
<b>Sent:</b> Tuesday, April 10, 2018 12:19 PM<br>
<b>To:</b> Chris Phillips <Chris.Phillips@csiro.au><br>
<b>Cc:</b> difxusers <difx-users@nrao.edu><br>
<b>Subject:</b> Re: [Difx-users] Difx on XEON Scalable Platform CPUs?<o:p></o:p></span></p>
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<p class="MsoNormal">Hi Walter<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"> When I had DiFX running on early versions of Xeon Phi (2012?) I had to by-pass the IPP libraries (at the time Intel said they were not keen to carry those forwards). So all functionality was included in GENERIC. Some things had to be inline
functions, but I could use the MKL libraries for others. <o:p></o:p></p>
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<p class="MsoNormal" style="background:white"><span style="font-family:"Arial",sans-serif;color:#222222">Has IPP been ported now? <o:p></o:p></span></p>
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<p class="MsoNormal"> If not (and maybe if so) it could be worth looking to see where the speed up would be (it was dominated by the complex multiply accumulate at the time) and see if that could be improved. For example the intrinsic for <span style="color:black">genericAddProduct_32fc
could be replaced with the code example in:</span><o:p></o:p></p>
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<span style="font-size:9.0pt;font-family:"Arial",sans-serif;color:#53575E">In <a href="https://software.intel.com/en-us/forums/intel-isa-extensions/topic/74737">https://software.intel.com/en-us/forums/intel-isa-extensions/topic/74737</a><o:p></o:p></span></p>
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<span style="font-size:9.0pt;font-family:"Arial",sans-serif;color:#53575E"> The comments include:<o:p></o:p></span></p>
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<span style="font-size:9.0pt;font-family:"Arial",sans-serif;color:#53575E">SSE3 (included in SSE4.2) has specific instructions which the compiler will use to vectorize complex without requiring intrinsics or shuffle. In order to use fully AVX2 or AVX512, as
John said, it will be necessary to split the data. Compilers will not attempt to evaluate whether a mixture of SSE3 and AVX2 will prove faster. The statistics produced by opt-report may help to evaluate this, and might lead you to use some SSE3 intrinsics
in case the overhead of splitting the data would be significant.<o:p></o:p></span></p>
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<span style="font-size:9.0pt;font-family:"Arial",sans-serif;color:#53575E"><o:p> </o:p></span></p>
<p style="mso-margin-top-alt:0cm;margin-right:0cm;margin-bottom:18.0pt;margin-left:0cm;background:white;word-wrap:break-word">
<span style="font-size:9.0pt;font-family:"Arial",sans-serif;color:#53575E">Page 5-26 of <a href="https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf">https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf</a>
may have useful examples as well<o:p></o:p></span></p>
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<p class="MsoNormal"> Richard<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">On Tue, Apr 10, 2018 at 9:20 AM, <<a href="mailto:Chris.Phillips@csiro.au" target="_blank">Chris.Phillips@csiro.au</a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal">Hi Walter<br>
<br>
No I haven’t, but just a note that when I tried DIFX on the KnightsLanding an year or so ago, IPP had not been ported to AVX512 at that stage<br>
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Cheers<br>
<span class="gmail-m7810411253554822398hoenzb"><span style="color:#888888">Chris</span></span><o:p></o:p></p>
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<br>
> On 10 Apr 2018, at 11:15, Walter Brisken <<a href="mailto:wbrisken@lbo.us" target="_blank">wbrisken@lbo.us</a>> wrote:<br>
><br>
><br>
> Hi DiFX Users,<br>
><br>
> I'm wondering if anyone on this list has tried DiFX on Intel XEON CPUs called "Scalable Platform". These are distinguished by "bronze", "silver", "gold", or "platinum" varieties. They are also labeled as "Skylake-SP" processors. If anyone has such experience,
I'm wondering if any benchmarks are available. Also wondering if any attempt to evaluate improvement the AVX512 instructions offer in DiFX computing.<br>
><br>
> Thanks,<br>
><br>
> Walter<br>
><br>
> --<br>
> -------------------------<br>
> Walter Brisken<br>
> Director<br>
> Long Baseline Observatory<br>
> (575)-835-7133 (office)<br>
> (505)-234-5912 (cell)<br>
><br>
> _______________________________________________<br>
> Difx-users mailing list<br>
> <a href="mailto:Difx-users@listmgr.nrao.edu" target="_blank">Difx-users@listmgr.nrao.edu</a><br>
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https://listmgr.nrao.edu/mailman/listinfo/difx-users</a><br>
<br>
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<p class="MsoNormal">-- <o:p></o:p></p>
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<p class="MsoNormal">-------------------------<br>
Dr Richard Dodson,<br>
International Centre for Radio Astronomy Research<br>
University of Western Australia<br>
P: +8 6488 7842 E: <a href="mailto:richard.dodson@icrar.org" target="_blank">richard.dodson@icrar.org</a><o:p></o:p></p>
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